From ucbvax.Berkeley.EDU!pixar!gbuce Fri Jan 27 22:06:10 1989
Date: Fri, 27 Jan 89 18:59:13 -0800
From: pixar!gbuce@ucbvax.Berkeley.EDU (George Buce)
To: gpu.utcs.toronto.edu!anakin@ucbvax.Berkeley.EDU
Subject: LUCAS

                                                        George Buce
                                                        Pixar
                                                        Marin County, CA
                                                        ucbvax!pixar!gbuce

Brad Fowles
Anakin
Toronto CAN
anakin@utcs.toronto.edu

Dear Brad:

Well, the U9 fix seems to work.  The problem seems to be in the area where you
try to re-generate C1* + C3* by using 7MB2.  The problem stems from the fact 
that there is no way to know if the regenerated signal is low during S1 and S5 
or if it is low during S3 and S7, since the 7MB2 signal starts up at a random 
state.  What I had proposed to you in my previous note is to somehow sync up 
7MB2 with the falling edge of 68000 S5, possibly by using the first DTACK* from
the system.  Well, that's exactly what I did.  Since we know that the first
DTACK* comes from within the Amiga during the call to ROM directly after reset,
and the Amiga specs state that you aren't allowed to return DTACK* before the
beginning of S4, we know that the DTACK signal will fall somewhere during the
S4 state.  What my fix does it to hold the 7MB2 flip-flop in a preset state
(with the 7MB2 signal going into U6 held low) until the first occurence of
DTACK*'s falling edge.  The 7MB2 is then allowed to free run starting with the
rising edge of 7M at the beginning of S6.  This guarantees that we will
correctly generate C1* + C3* by ORing 7M and 7MB2.  

(Schematic follows...)

The fix consists of a piggy back 74LS74 over the U9 74x74.  I first bent up pin 
10 of the bottom (U9) 74x74.  I then clipped pins 5, 6 and 9 of the top 74LS74
and bent up pins 8, 10, 11 and 12.  The remaining pins of the top 74LS74 are
soldered directly to the corresponding pins of the bottom U9 74x74.  These pins
should be pins 1, 2, 3, 4, 7, 13 and 14.  Pin 10 of the bottom U9 74x74 should
be connected to pin 8 of the piggyback 74LS74.  (I just bent the pins together
(veeery carfully!) but you may want to use a small wire.)  Pin 12 is tied to
ground (on the chip stack is easiest).  At the 68000 socket, DTACK* (pin 10?) is
tapped into and run to the unused inverter at U10, pin 9.  The output at U10,
pin 8 is run to the DTACK input on the piggyback flip-flop (called U12 from
here on) pin 11.  The 68000 RESET* (pin 18?) line is tapped into and run to U12,
pin 10.  This fix does not require any cuts to the main circuit board, so it's 
always easy to undo.


                                      --------------- 
                                     |      +5V      |
                                     |       |       |
                                     |     13|       |
                                     |    -------    |
                                     | 12|   C   |9  |
                                     ----|D     Q|-  |
                                       11|  U9b _|8  |
                                  7M ----|>     Q|---+---- 7MB2
                                         |   P   |
                                          -------
                             +5V           10|  74F74
                              |              |
                            13|              |
                           -------           |
                        12|   C   |9         |
            U10    GND----|D     Q|-         |
_____       |\          11|  U12b_|8         |
DTACK------O| >-----------|>     Q|----------
          9 |/  8         |   P   |
            74F04          ------- 
                            10|  74LS74
            _____             |
            RESET-------------


Theory of Operation:

The theory of operation is rather straightforward.  Upon system RESET, the
flip-flop at U12 is preset so that the Q* output at pin 8 is low.  This presets
U9b so that the Q* output (named 7MB2) is low.  Having 7MB2 remain low means
that the DTPRELIM* signal will be generated everytime the 7MHz clock is low.
The first DTACK* from the Amiga will arrive during 68000 state S4, permitting
DTTRIG* to be generated during S5.  The first DTACK* will also clock in a zero
on U12, releasing the RESET line on U9. This will permit 7MB2 to continue
operating normally from that point on, remaining in sync with 68000 state S5 as
is needed to synchronise the 68020 with the 68000.

If you recall, I could only get the LUCAS board to boot up with a 12MHz xtal
and a 74HC74.  I took two 74LS74s for this piggyback fix and had no problem
booting up at 20MHz.  As far as using 74LS parts, I don't see any reason why a
part any faster than 74LS would be needed.  Since the 7MB2 signal is rather
slow and we don't care how slow the piggyback U12 responds to DTACK*, the only
question that remains is whether or not U9a latching SYSDSACK1* is fast enough.
The arrival of the DTTRIG* signal is totally asynchronous to the 16M clock, so
if it arrives a little after the setup time for U9a, we'll miss it until the
next rising edge of 16M.  That's probably the safest thing to do, since 
otherwise the DSACKx* to DATA valid timing will be a little tight...  I just 
recieved the latest on the LUCAS board concerning DMA access (and eliminating 
the synchronization on the R/W line).  If that half a flip-flop will be unused,
people could avoid a piggyback fix by using the abandoned R/W flip-flop.  (BTW,
thanks for not tying the unused input on the 'F04 inverter to power or ground.
That made this a "no cuts" fix 8{)...)

Tomorrow I'll subject my Amiga to the bus analyzer to see what kind of timing
my memory board(s) generate to see if I can create another fix...

I'm not posting this to the net until you've got a good look at it.  I'm quite
confident that this will work for everyone, but I'd prefer to see it on the
bus analyzer before I sign the note in blood.  If you agree with the change,
feel free to post it on all the nets (I only have access to UUCP).

                                           George Buce (8{>



